The present invention relates to a logic integrated circuit. In particular, the present invention relates to a self-driven, synchronous rectification scheme for a power converter which is easily adapted to various circuit topologies.
There is an ever-increasing demand in the power electronics market for low voltage and high current DCxe2x80x94DC converters. As output voltage is desired to be 3.3V or lower, even a state-of-the-art schottky diode with a forward voltage drop of 0.3V has an unacceptable amount of power loss.
Because of this, synchronous rectifiers are often used to improve the efficiency of DCxe2x80x94DC converters. Generally, there are two types of synchronous rectifiers, self-driven and externally driven. Since the self-driven mode is usually less complex, less costly and more reliable, it is preferred for use with most low voltage DCxe2x80x94DC converter applications.
FIG. 1A illustrates a conventional self-driven synchronous rectification, asymmetrical, zero voltage switching (ZVS) half-bridge (HB) topology. Although this circuit is very simple, it is only suitable for applications where the output voltage is in the range of from about 3.3V to 6V. Referring to FIG. 1B, the gate-drive voltages Vgs3 and Vgs4 of synchronous rectifiers S3 and S4, respectively, are as follows:                               V          gs3                =                                                            2                ⁢                                  N                  s                                                            N                p                                      ⁢                          DV              in                                =                                                    2                N                            ⁢                              DV                in                                      =                                                            V                  0                                                  1                  -                  D                                            ⁢                              xe2x80x83                            ⁢                              (                                                      t                    0                                    ≤                  t                  ≤                                      t                    1                                                  )                                                                        (        1        )                                          V          gs4                =                                                            2                ⁢                                  N                  s                                                            N                p                                      ⁢                          (                              1                -                D                            )                        ⁢                          V              in                                =                                                                      2                  ⁢                                      (                                          1                      -                      D                                        )                                                  N                            ⁢                              V                in                                      =                                                            V                  0                                D                            ⁢                              xe2x80x83                            ⁢                              (                                                      t                    1                                    ≤                  t                  ≤                                      t                    2                                                  )                                                                        (        2        )            
wherein, Vin is the input voltage; Vo is the output voltage; D is the steady-state duty cycle; Np is the number of primary winding turns of the transformer; Ns is the number of secondary turns of the transformer; and N is the turns ratio of the transformer. The turns ratio of the transformer TR is calculated by dividing the number of primary windings by the number of secondary windings (i.e. N=Np/Ns).
FIG. 1B illustrates the switching waveform occurring in the converter illustrated in FIG. 1A. As shown in FIG. 1B, the gate-drive voltage Vgs4 of S4 is always higher than the gate-drive voltage Vgs3 of S3 if D is less than 50%. If we assume that the minimum steady-state duty cycle D at heavy load is 30%, then Vgs3 is about 1.4V, and Vgs4 is about 3.3V. Since most synchronous rectifiers (including logic level devices) only work well with the gate-drive voltage between about 4V and 20V, the circuit shown in FIG. 1A only works well when the output voltage VO is between 2.9V to 6V. If the output voltage is below 2.9V, S3 would be under driven. If the output voltage were about 6V, then S4 would be over driven. In either case the synchronous rectifiers are easily rendered inoperative.
Accordingly, there remains a need for a self-driven synchronous rectifier which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.
The self-driven synchronous rectification circuit of the present invention includes two power switches S1 and S2; a transformer Tr having a primary winding with Np number of turns, a secondary winding with Ns number of turns and an auxiliary winding with Na number of turns; two secondary synchronous rectifiers S3 and S4; two diodes D1 and D2; and two zener diodes ZD1 and ZD2.
The number of auxiliary winding turns Na of the transformer Tr ensure that the synchronous rectifiers S3 and S4 are supplied with an adequate gate-drive voltage. The selection of the number of auxiliary winding turns for use is determined according to the output voltage required. In the circuit of the present invention, when S3 conducts, the gate-drive voltage of S4 is clamped by D1. Also, when S4 conducts, the gate-drive voltage of S3 is clamped by D2. In other words, D1 and D2 prevent S3 and S4 from conducting at the same time. ZD1 and ZD2 restrain the gate overvoltage of S3 and S4, respectively.
With the above circuit configuration, a self-driven synchronous rectification scheme can be implemented which operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.